root/mmu.h

/*   */

INCLUDED FROM

   1 // This file contains definitions for the
   2 // x86 memory management unit (MMU).
   3 
   4 // Eflags register
   5 #define FL_IF           0x00000200      // Interrupt Enable
   6 
   7 // Control Register flags
   8 #define CR0_PE          0x00000001      // Protection Enable
   9 #define CR0_WP          0x00010000      // Write Protect
  10 #define CR0_PG          0x80000000      // Paging
  11 
  12 #define CR4_PSE         0x00000010      // Page size extension
  13 
  14 // various segment selectors.
  15 #define SEG_KCODE 1  // kernel code
  16 #define SEG_KDATA 2  // kernel data+stack
  17 #define SEG_UCODE 3  // user code
  18 #define SEG_UDATA 4  // user data+stack
  19 #define SEG_TSS   5  // this process's task state
  20 
  21 // cpu->gdt[NSEGS] holds the above segments.
  22 #define NSEGS     6
  23 
  24 #ifndef __ASSEMBLER__
  25 // Segment Descriptor
  26 struct segdesc {
  27   uint lim_15_0 : 16;  // Low bits of segment limit
  28   uint base_15_0 : 16; // Low bits of segment base address
  29   uint base_23_16 : 8; // Middle bits of segment base address
  30   uint type : 4;       // Segment type (see STS_ constants)
  31   uint s : 1;          // 0 = system, 1 = application
  32   uint dpl : 2;        // Descriptor Privilege Level
  33   uint p : 1;          // Present
  34   uint lim_19_16 : 4;  // High bits of segment limit
  35   uint avl : 1;        // Unused (available for software use)
  36   uint rsv1 : 1;       // Reserved
  37   uint db : 1;         // 0 = 16-bit segment, 1 = 32-bit segment
  38   uint g : 1;          // Granularity: limit scaled by 4K when set
  39   uint base_31_24 : 8; // High bits of segment base address
  40 };
  41 
  42 // Normal segment
  43 #define SEG(type, base, lim, dpl) (struct segdesc)    \
  44 { ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff,      \
  45   ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1,       \
  46   (uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 }
  47 #define SEG16(type, base, lim, dpl) (struct segdesc)  \
  48 { (lim) & 0xffff, (uint)(base) & 0xffff,              \
  49   ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1,       \
  50   (uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 }
  51 #endif
  52 
  53 #define DPL_USER    0x3     // User DPL
  54 
  55 // Application segment type bits
  56 #define STA_X       0x8     // Executable segment
  57 #define STA_W       0x2     // Writeable (non-executable segments)
  58 #define STA_R       0x2     // Readable (executable segments)
  59 
  60 // System segment type bits
  61 #define STS_T32A    0x9     // Available 32-bit TSS
  62 #define STS_IG32    0xE     // 32-bit Interrupt Gate
  63 #define STS_TG32    0xF     // 32-bit Trap Gate
  64 
  65 // A virtual address 'la' has a three-part structure as follows:
  66 //
  67 // +--------10------+-------10-------+---------12----------+
  68 // | Page Directory |   Page Table   | Offset within Page  |
  69 // |      Index     |      Index     |                     |
  70 // +----------------+----------------+---------------------+
  71 //  \--- PDX(va) --/ \--- PTX(va) --/
  72 
  73 // page directory index
  74 #define PDX(va)         (((uint)(va) >> PDXSHIFT) & 0x3FF)
  75 
  76 // page table index
  77 #define PTX(va)         (((uint)(va) >> PTXSHIFT) & 0x3FF)
  78 
  79 // construct virtual address from indexes and offset
  80 #define PGADDR(d, t, o) ((uint)((d) << PDXSHIFT | (t) << PTXSHIFT | (o)))
  81 
  82 // Page directory and page table constants.
  83 #define NPDENTRIES      1024    // # directory entries per page directory
  84 #define NPTENTRIES      1024    // # PTEs per page table
  85 #define PGSIZE          4096    // bytes mapped by a page
  86 
  87 #define PTXSHIFT        12      // offset of PTX in a linear address
  88 #define PDXSHIFT        22      // offset of PDX in a linear address
  89 
  90 #define PGROUNDUP(sz)  (((sz)+PGSIZE-1) & ~(PGSIZE-1))
  91 #define PGROUNDDOWN(a) (((a)) & ~(PGSIZE-1))
  92 
  93 // Page table/directory entry flags.
  94 #define PTE_P           0x001   // Present
  95 #define PTE_W           0x002   // Writeable
  96 #define PTE_U           0x004   // User
  97 #define PTE_PS          0x080   // Page Size
  98 
  99 // Address in page table or page directory entry
 100 #define PTE_ADDR(pte)   ((uint)(pte) & ~0xFFF)
 101 #define PTE_FLAGS(pte)  ((uint)(pte) &  0xFFF)
 102 
 103 #ifndef __ASSEMBLER__
 104 typedef uint pte_t;
 105 
 106 // Task state segment format
 107 struct taskstate {
 108   uint link;         // Old ts selector
 109   uint esp0;         // Stack pointers and segment selectors
 110   ushort ss0;        //   after an increase in privilege level
 111   ushort padding1;
 112   uint *esp1;
 113   ushort ss1;
 114   ushort padding2;
 115   uint *esp2;
 116   ushort ss2;
 117   ushort padding3;
 118   void *cr3;         // Page directory base
 119   uint *eip;         // Saved state from last task switch
 120   uint eflags;
 121   uint eax;          // More saved state (registers)
 122   uint ecx;
 123   uint edx;
 124   uint ebx;
 125   uint *esp;
 126   uint *ebp;
 127   uint esi;
 128   uint edi;
 129   ushort es;         // Even more saved state (segment selectors)
 130   ushort padding4;
 131   ushort cs;
 132   ushort padding5;
 133   ushort ss;
 134   ushort padding6;
 135   ushort ds;
 136   ushort padding7;
 137   ushort fs;
 138   ushort padding8;
 139   ushort gs;
 140   ushort padding9;
 141   ushort ldt;
 142   ushort padding10;
 143   ushort t;          // Trap on task switch
 144   ushort iomb;       // I/O map base address
 145 };
 146 
 147 // Gate descriptors for interrupts and traps
 148 struct gatedesc {
 149   uint off_15_0 : 16;   // low 16 bits of offset in segment
 150   uint cs : 16;         // code segment selector
 151   uint args : 5;        // # args, 0 for interrupt/trap gates
 152   uint rsv1 : 3;        // reserved(should be zero I guess)
 153   uint type : 4;        // type(STS_{IG32,TG32})
 154   uint s : 1;           // must be 0 (system)
 155   uint dpl : 2;         // descriptor(meaning new) privilege level
 156   uint p : 1;           // Present
 157   uint off_31_16 : 16;  // high bits of offset in segment
 158 };
 159 
 160 // Set up a normal interrupt/trap gate descriptor.
 161 // - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate.
 162 //   interrupt gate clears FL_IF, trap gate leaves FL_IF alone
 163 // - sel: Code segment selector for interrupt/trap handler
 164 // - off: Offset in code segment for interrupt/trap handler
 165 // - dpl: Descriptor Privilege Level -
 166 //        the privilege level required for software to invoke
 167 //        this interrupt/trap gate explicitly using an int instruction.
 168 #define SETGATE(gate, istrap, sel, off, d)                \
 169 {                                                         \
 170   (gate).off_15_0 = (uint)(off) & 0xffff;                \
 171   (gate).cs = (sel);                                      \
 172   (gate).args = 0;                                        \
 173   (gate).rsv1 = 0;                                        \
 174   (gate).type = (istrap) ? STS_TG32 : STS_IG32;           \
 175   (gate).s = 0;                                           \
 176   (gate).dpl = (d);                                       \
 177   (gate).p = 1;                                           \
 178   (gate).off_31_16 = (uint)(off) >> 16;                  \
 179 }
 180 
 181 #endif

/*   */