(Many of these articles
are from digitimes.com.
For context, note the Wikipedia Silicon article implying that
10 nm is approximately from 48 to 90 silicon atoms laid end-to-end.
3 nm is approximately from 14 to 27 silicon atoms laid end-to-end.)
-
Taiwan must run faster in IC development: Q&A with science minister Chen Liang-gee
- TSMC to tape out first 5nm chip design
in 1H19
- AMEC 5nm plasma etching tools verified by TSMC
- Yangtze Memory gearing up for transition to 128-layer 3D NAND
- Hema Supermarket realizes
new retail concept (not about chips, but fascinating:
In a two-year old Shanghai-based supermarket chain of Alibaba, they
have delivery to home 30 minutes after order online; restaurant
to eat while robots based on automated guided vehicles deliver
your food to you)
- Samsung, SK Hynix stepping up DRAM EUV technology R&D
- Samsung starts production of 7LPP with EUV
- Robots with eyes and brains reshaping manufacturing, says Solomon Technology chairman
- Taiwan partners to gain from Xilinx 7nm FPGA rollout in 2019
- TSMC 7nm, 5nm to enjoy strong demand for AI chips
- Intel 10nm delay raises speculation of foundry business scale-down
- Competition heats up in advanced IC process, equipment deployments
- DRAM transition to EUV for sub-10nm node remains a financial challenge
- Moore's Law has come to its end, says Nvidia CEO Jensen Huang
- TSMC 3nm fab plan to create huge biz
opportunities for supply chains
-
Qualcomm, MediaTek yet to advance to 7nm node
("Apple and Samsung are expected to be the only two smartphone
vendors and chip developers who will remain keen to use 7nm
processes for making their chips in 2018 .... The sources
estimated that for a smartphone chipset maker, annual shipments
of 120-150 million chips fabricated on 7nm process are required
to secure a break-even against the development cost, and only
Apple, Samsung, Qualcomm and MediaTek can achieve that.")