Node:Simulation options, Next:Debugging VHDL programs, Previous:Simulation and run time, Up:Simulation and run time
In most system environments, it is possible to pass options while invoking a program. Contrary to most programming language, there is no standard method in VHDL to obtain the arguments or to set the exit status.
In GHDL, it is impossible to pass parameters to your design. A later version could do it through the generics interfaces of the top entity.
However, the GHDL run time behaviour can be modified with some options; for example, it is possible to stop simulation after a certain time.
The exit status of the simulation is EXIT_SUCCESS
(0) if the simulation completes, or EXIT_FAILURE
(1) in case of error (assertion failure, overflow or any constraint error).
Here is the list of the most useful options. Some debugging options are also available, but not described here. The --help
options lists all options available, including the debugging one.
--assert-level=LEVEL
severity_level
enumerated type defined in the standard
package or the none
name.
By default, only assertion violation of severity level failure
stops the simulation.
For example, if LEVEL was warning
, any assertion violation with severity level warning
, error
or failure
would stop simulation, but the assertion violation at the note
severity level would only display a message.
--assert-level=none
prevents any assertion violation to stop simulation.
--stop-time=TIME
For examples:
$ ./my_design --stop-time=10ns $ ./my_design --stop-time=ps
--stop-delta=N
--disp-time
--disp-tree[=KIND]
none
inst
proc
inst
but also display processes.port
proc
but display ports and signals too.
port
mode.--vcd=FILENAME
-
, then the standard output is used, otherwise a file is created or overwritten.
VCD (value change dump) is a file format defined by the verilog
standard and used by virtually any wave viewer.
Since it comes from verilog
, only a few VHDL types can be dumped. GHDL dumps only signals whose base type is of the following:
std.standard
package:
bit
bit_vector
ieee.std_logic_1164
package:
std_ulogic
std_logic
(because it is a subtype of std_ulogic
)
std_ulogic_vector
std_logic_vector
I have successfully used gtkwave
to view VCD files.
It is very unfortunate there is no standard or well-known wave file format supporting VHDL types. If you are aware of such a free format, please mail me (see Reporting bugs).
--sdf=PATH=FILENAME
--sdf=min=PATH=FILENAME
--sdf=typ=PATH=FILENAME
--sdf=max=PATH=FILENAME
PATH is a path of instances, separated with .
or /
. Any separator can be used. Instances are component instantiation labels, generate labels or block labels. Currently, you cannot use an indexed name.
If the option contains a type of delay, that is min=
, typ=
or max=
, the annotator use respectively minimum, typical or maximum values. If the option does not contain a type of delay, the annotator use the typical delay.
See Backannotation, for more details.
--stack-max-size=SIZE
If the value SIZE is followed (without any space) by the k
, K
, kb
, Kb
, ko
or Ko
multiplier, then the size is the numeric value multiplied by 1024.
If the value SIZE is followed (without any space) by the m
, M
, mb
, Mb
, mo
or Mo
multiplier, then the size is the numeric value multiplied by 1024 * 1024 = 1048576.
Each non-sensitized process has its own stack, while the sensitized processes share the same and main stack. This stack is the stack created by the operating system.
Using too small stacks may result in simulation failure due to lack of memory. Using too big stacks may reduce the maximum number of processes.
--stack-size=SIZE
The stack of the non-sensitized processes grows until reaching the maximum size limit.
--help