Samsung Electronics has begun mass producing 10nm-class, 8Gb DDR4 DRAM chips and modules derived from them, according to the company.
Samsung claimed it opened the door to "10nm-class DRAM" for the first time in the industry after overcoming technical challenges in DRAM scaling. These challenges were mastered using currently available ArF (argon fluoride) immersion lithography, free from the use of EUV (extreme ultraviolet) equipment.
"Samsung's 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry," said Young-Hyun Jun, president of Samsung's memory business. "In the near future, we will also launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users."
Samsung's 10nm-class 8Gb DDR4 DRAM significantly improves the wafer productivity of 20nm 8Gb DDR4 DRAM by more than 30%, the company indicated. The new DRAM supports a data transfer rate of 3,200Mbps, which is more than 30% faster than the 2,400Mbps rate of 20nm DDR4 DRAM. Also, new modules produced from the 10nm-class DRAM chips consume 10-20% less power, compared to their 20nm-process-based equivalents, which will improve the design efficiency of next-generation, high-performance computing (HPC) systems and other large enterprise networks, as well as being used for the PC and mainstream server markets.
The 10nm-class DRAM is the result of Samsung's advanced memory design and manufacturing technology integration, the company noted. To achieve an extremely high level of DRAM scalability, Samsung has taken its technological innovation one step further than what was used for 20nm DRAM. Key technology developments include improvements in proprietary cell design technology, QPT (quadruple patterning technology) lithography, and ultra-thin dielectric layer deposition.
Unlike NAND flash memory, in which a single cell consists of only a transistor, each DRAM cell requires a capacitor and a transistor that are linked together, usually with the capacitor being placed on top of the area where the transistor rests. In the case of the new 10nm-class DRAM, another level of difficulty is added because they have to stack very narrow cylinder-shaped capacitors that store large electric charges, on top of a few dozen nanometer-wide transistors, creating more than eight billion cells.
Samsung successfully created the new 10nm-class cell structure by utilizing a proprietary circuit design technology and quadruple patterning lithography. Through quadruple patterning, which enables use of existing photolithography equipment, Samsung also built the core technological foundation for the development of the next-generation 10nm-class DRAM.
In addition, the use of a refined dielectric layer deposition technology enabled further performance improvements in the new 10nm-class DRAM. Samsung engineers applied ultra-thin dielectric layers with unprecedented uniformity to a thickness of a mere single-digit angstrom (one 10 billionth of a meter) on cell capacitors, resulting in sufficient capacitance for higher cell performance.
Based on its advancements with the new 10nm-class DDR4 DRAM, Samsung expects to also introduce a 10nm-class mobile DRAM solution with high density and speed later in 2016, which will further solidify its leadership in the ultra-HD smartphone market.
While introducing a wide array of 10nm-class DDR4 modules with capacities ranging from 4GB for notebooks to 128GB for enterprise servers, Samsung will be extending its 20nm DRAM line-up with its new 10nm-class DRAM portfolio throughout the year.