For a very nice description of cache coherence on the web, see "Computer Architecture --- Cache Coherence" (by Morris, includes a state transition diagram for MESI within the page).

The MESI diagram from the above article is available by itself.

The web page by Morris is part of an excellent evolving set of notes: Computer Architecture: The Anatomy of Modern Processors.

A related set of course notes by Devadas is available on the Web from MIT.

  • Here is a glimpse of the real world: Sun Enterprise 10000 (64-way SMP)