Homework 1
		EXTENSION:  due Thurs., Jan. 23

> > I've talked with the grader now.  He is requesting hardcopy (printouts)
> > for hw1.  As I explained, the on-line submission is the time stamp.
> > If you submitted on-line on time, then hw1 is on time.
> > 
> > In addition, please print out:
> > 1.  Your English writeup (with any graphs, if you created them)
> > 2.  The raw output of your program.  [You do not need to print the program
> >       itself.  If the raw output is lengthy, and some parts are not
> >       needed for the conclusion, you can edit out those parts,
> >       leaving a comment:  [ INTERMEDIATE OUTPUT DELETED ]
> > 
> > Please either submit the hardcopy to my mailbox, or else bring
> > them to the next COM 3200 class.


For this assignment, you will write a program to measure the performance
specifications of a computer.  You must report both on a Pentium 4 computer
and on a SunBlade 100 computer from the CCS laboratory.  (You can discover
the hostnames by typing `computers' from a CCS account.  Since the
Pentium 4 computers are still new, they may not be listed.
Here are three of them:  the-wall@ccs.neu.edu, momentary-lapse@ccs.neu.edu,
meddle@ccs.neu.edu.)

Please note the file hw1-code in the instructor's directory.  That
consists of fragments of C code that you may find helpful in getting
the timing, and in creating random accesses to memory.

You must submit a tarred, gzipped directory with a file, REPORT.txt,
and a file with the code that you used to get your results.

You can submit from any CCS UNIX account as follows (assuming your
files are in a directory, hw1).
  tar cvf hw1.tar ./hw1
  gzip hw1.tar
  /course/com3200/submit-3200-hw1 hw1.tar.gz
[ Record the file name under which the submit script stores your hw1.
  You can delete that file and re-submit before the deadline if you want. ]

PART 1:
  Write a program that will estimate
a) the size of the L1 cache,
b) the size of the L2 cache,
c) the amount of DRAM,
d) the length of the L1 cache line,
e) the length of the L2 cache line,
f) the size of a bank of RAM within the DRAM chip,
g) the number of memory banks available in a single DRAM chip, and
h) the width of the memory bus, aka system bus (number of bits wide)

PART 2:
Report on:
a)  the memory bandwidth (MB/s) for sequential `int' accesses to RAM;
b)  the memory latency (ns) for a random access to RAM memory; and
c)  the random access memory bandwidth (the memory bandwidth seen
	when each `int' access is to a random location.

PART 3:
Report the data of PART 2 for the L1 cache (instead of RAM).

PART 4:
Report the data of PART 2 for the L2 cache (instead of RAM).

PART 5:
Report the data of PART 2 for the virtual memory (so that most new
  page accesses are page faults).

PART 6:
Report the number of TLB entries.
[ Caches hold real addresses, not virtual addresses.  The TLB (translation
  lookaside buffer) does the translation from a virtual page to a real
  page of RAM.  There are only a limited number of TLB registers.
  There is a measurable delay when the memory access pattern causes
  a TLB register to be re-used to map a different virtual memory page. ]

PART 7:
Describe the algorithms that you used to measure the above data.
Use formal, technical English.  Good style _does_ count.